Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with Magnetic Tunnel Junction (MTJ)s, is a major emerging technology, highly competitive with existing semiconductor memories (SRAM, DRAM, Flash etc). The MTJ consists of two ferromagnetic layers separated by a thin dielectric layer. Magnetization of the two ferromagnetic layers can be arranged to be in either parallel (low resistance) or anti-parallel (high resistance) magnetization states, representing “1” and “0” respectively,
The MTJ memory cells are usually inserted at the back end of a standard CMOS process. The high-speed version of MRAM architecture consists of a cell with an access transistor and a MTJ (1T1MTJ) in the array. The MTJ element is formed on top of the bottom conductor line, which is used to connect the base of the MTJ to the access transistor. Switching of the free layer magnetization in the MTJ device is accomplished by applying currents to orthogonal conductor lines.
The conductors are arranged in a cross-point architecture that provides the field for selectively switching each bit. One line (bit line) provides the field parallel to the easy axis of the bit, while another line (write word line) provides the perpendicular (hard axis) component of the field. The intersection of the lines generates a peak field that is engineered to be just above the switching threshold of that MTJ. For high performance MTJ devices, the separation between the write word line (bit line) and MTJ free layer is made as small as possible.
In a read operation, the read word line (RWL) is selected, and the transistor is turned on. This causes the MTJ device to be connected to ground. At this time, a sense current passes through the BL-MTJ-BE and to ground. The resistance of the MTJ device is low when the MTJ is storing a 1 and high when it is storing a 0.
Referring now to FIG. 1a, shown there is tantalum hard mask 15 which will be used to separate MTJ sheet stack 16 into individual devices, each resting on a bottom electrode that comprises material from layer 17 which rests on SiN ILD 11. Also seen (though not relevant to the invention) are vias 18. In FIG. 1b, layer 16 has been patterned into individual MTJ devices 4, with Ta mask 15 having been partly consumed during the etch operation. In FIG. 1c bottom electrode layer 17 has also been patterned into individual electrodes. However, in the course of making certain that said electrodes are truly electrically isolated one from another, ILD layer has been over etched so that its top surface has been partly eroded, as symbolized by its being shown as a broken line in the figure.
Reactive ion etching (RIE) has been preferred over IBE (ion beam etching) as the method for etching layer 17. However, vertical features created by IBE always have an extended slope on the edge, which not only could creates electrical shorting problems but also limits further reduction of line width and make it impossible to make very high density IC device. In general, RIE is considered a better approach to creating well-defined three dimensional micro-features but there are several major problems currently associated with the RIE process:
(I) The uncontrollable over etch mentioned above is due to the lack of etching selectivity between the bottom electrode and the ILD. FIG. 2 illustrates the structure of layer 17 in greater detail—immediately on ILD 11 is TaN layer 12 on which is alpha tantalum layer 13. Layer 14 comprises a second TaN layer.(2) This etching process always results in a large amount of re-deposition all over the surface of the device due to the non-volatility of the reaction products.(3) The MTJ will experience two etching processes (first in its own etch and then during the BE etch). This not only affects the MTJ's overall dimensions, but also results in serious damage to the edge of the MTJ's tunnel barrier layer.
A routine search of the prior art was performed with the following references of interest being found:
U.S. Pat. No. 6,974,708 (Horng et al) discloses OSL on top of the bottom electrode.
U.S. Pat. No. 6,703,654 (Horng et al) teaches a NiCr/Ru bottom electrode.
U.S. Pat. No. 6,960,48 (Horng et al) discloses a bottom electrode of /NiCr/Ru/α-Ta.
U.S. Patent Application 2005/0254293 (Horng et al) teaches layers comprising NiCr/Ru/αTa.
U.S. Patent Application 2005/0016957 (Kodaira et al), the Anelva Co., shows dry etching using CH3OH.
U.S. Patent Application 2006/0002184 (Hong et al) teaches bottom electrodes of NiCr/Ru/Ta or NiCr/Ru/α-TaN.
Other references, supplied by the inventor, are:
    1. S. Tehrani et. al. “Magnetoresistive Random Access Memory using Magnetic tunnel junction” Proceeding of the IEEE. Vol. 91, p 703-712, 2003.    2. C. Horng et. al. HTO3-022 “A novel structure/method to fabricate a high performance magnetic tunneling junction MRAM”. Magic touch and NiCr/Ru/alpha-Ta.    3. “Nanoscale MRAM elements” (including an extensive review of RIE), —S. J. Peraton and J. R. Childress (IBM and U of F).